The present description relates to slicer circuits used in decision feedback equalizer (DFE) circuit implementations.
Digital receivers operate by sampling an analog waveform and detecting the sampled data. Signals arriving at a receiver are typically corrupted by crosstalk, echo, inter-symbol interference (ISI), and other noise. As a result, a receiver must equalize the channel to compensate for signal corruption and also decode the encoded signal. Decision feedback equalization, which may for example employ a nonlinear equalizer to equalize the channel using a feedback loop based on previously decided symbols, can be used to remove ISI and other noise. Some DFE configurations use slicers to quantize a signal to a binary “1” or “0” based on the sampled value and a slicer threshold. Conventionally, a slicer designed to perform signal equalization and quantization to generate S-bit output of a N-tap look-ahead DFE requires at least 2*(2S*N) adders/subtractors. For example, to generate 2-bit output symbols for a 2-tap look-ahead DFE, a slicer would normally be required to compute 32 parallel additions/subtractions. Since adders are a main source of timing bottlenecks in DSP circuits, using too many layers of adders for circuit implementations can result in a slicer with long critical path. As a consequence, registers are required to pipeline the slicer circuit, adding more hardware resources to the design.
Accordingly, there is a need for improved slicer circuit architecture for use in decision feedback equalizer circuit implementations.